High emulation performance
Siemens’ Veloce CS selected by Arm for Neoverse Compute Subsystems verification and validation
Wednesday, 16. July 2025
| Redaktion
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Veloce Strato CS delivers high emulation performance, maintains fast full visibility debug, and scales from 40 million gates (MG) to 40 billion gates (BG)
Veloce Strato CS delivers high emulation performance, maintains fast full visibility debug, and scales from 40 million gates (MG) to 40 billion gates (BG), Photo: Siemens

Siemens Digital Industries Software today announced that Veloce Strato CS and Veloce proFPGA CS have been deployed at Arm, a longtime user of Veloce, as part of its design flow for Arm Neoverse Compute Subsystems (CSS). "Time to market is increasingly in focus for our partner ecosystem and critical to remaining competitive in this era of computing,” stated Karima Dridi, Head of Productivity Engineering, Arm. “A core component of Arm Neoverse CSS is the pre-validation and verification, made possible by adopting innovative new tools like Siemens Veloce CS system, so that our partners can get their silicon solutions to market faster.”

“We are delighted to extend our collaboration with Arm to the Veloce CS system. Veloce Strato CS with the Veloce PCIe Composite Device is delivering outstanding emulation performance improvements with unique and demonstrated capacity scaling, and Veloce proFPGA CS with AMD VP1902 Adaptive SoC is providing a fast and scalable prototyping solution,” said Jean-Marie Brunet, vice president and general manager, Hardware-Assisted Verification, Siemens Digital Industries Software. “With the Veloce CS system we address the varied challenges faced by hardware, software, and system engineers. Our longstanding relationship with Arm gives us a strong foundation for gauging their needs and the dynamics of their business as market requirements change.”

The Veloce CS system is available in a modular, blade-based configuration that is fully compliant with modern datacenter requirements for easy installation, very low power consumption, superior cooling, and compact footprint. Veloce proFPGA CS is also offered as a desktop lab version for additional user flexibility. Veloce Strato CS delivers high emulation performance, maintains fast full visibility debug, and scales from 40 million gates (MG) to 40 billion gates (BG). Veloce PCIe composite device (PCD) technology is an emulation solution suite designed to help verify customer IP within Arm CSS. The PCD technology integrates Arm Compliance Suite (ACS), PCIe and NVMe, in one unified system visualization and debug environment enabled by Veloce Protocol Analyzer.

Veloce proFPGA CS delivers a fast and comprehensive software prototyping solution, scaling from one FPGA (VP 1902) to hundreds of FPGAs. Its high performance, together with its highly flexible and modular design, helps customers dramatically accelerate firmware, operating system, application development, and system integration tasks.

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